Aditya Engineering College - [AEC] M.Tech Vlsi Design: Fees 2026, Course Duration, Dates, Eligibility

Ans. GATE EC (Electronics and Communication Engineering) is the primary paper for M.Tech VLSI Design. A valid EC score qualifies for GATE-based admission and AICTE-PG scholarship eligibility. Candidates from EE or IN paper backgrounds may also be considered; confirm at adityauniversity.in.

Ans. Yes. GATE EC-qualified full-time M.Tech students at AICTE-approved institutions are eligible for Rs. 12,400 per month. With total fees of Rs. 1.65 Lakhs over two years, the scholarship covers the entire tuition within the first semester. Verify current scholarship rules at aicte-india.org.

Ans. Graduates can pursue roles as VLSI design engineers, FPGA engineers, verification engineers, and SoC architects at semiconductor companies, EDA tool vendors, and electronics OEMs. Companies such as Qualcomm, Texas Instruments, Intel, ISRO, and DRDO recruit M.Tech ECE graduates with VLSI specialisation. The semiconductor sector in India is growing rapidly with Chips to Startup (C2S) and PLI scheme investments.

Ans. AEC's ECE department has VLSI and embedded systems labs equipped for digital design and FPGA implementation. Common EDA tools used in academic programmes include Cadence, Synopsys Design Vision, Xilinx Vivado, and ModelSim. For specific tool availability at AEC, contact the department at adityauniversity.in or visit the campus.

Ans. Yes. ISRO and DRDO recruit M.Tech graduates from UGC-recognised universities for scientist and engineer posts. A GATE EC score strengthens your eligibility for PSU and defence R&D recruitment. VLSI and embedded systems expertise is directly relevant to ISRO's satellite electronics and DRDO's defence electronics divisions.