Manav Rachna University Faridabad Bachelor of Technology [B.Tech] ECE {Hons.}(Lateral Entry) - VLSI Design & Verification in Association with Truechip: Fees 2026, Course Duration, Dates, Eligibility

Faridabad, HaryanaPrivate UniversityEstd 2004NAAC Grade A++
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Collegedunia Team

Content Curator | Updated 3+ months ago

B.Tech {Hons.} Electronics and Communication Engineering - VLSI Design & Technology at Manav Rachna University Faridabad is a 4 years, Full Time Degree program offered On Campus.

  • The total fees for the B.Tech {Hons.} Electronics and Communication Engineering - VLSI Design & Technology program at Manav Rachna University Faridabad is ₹ 10.26 Lakhs.
  • Students need to pay ₹ 2.57 Lakhs in the first year.

According to Collegedunia Engineering Ranking 2025, Manav Rachna University Faridabad ranks 312 out of 762 colleges in India with an overall score of 881 out of 2000. India Today Engineering ranking 2025, ranks Manav Rachna University Faridabad at 74 out of 269 in India.

Find detailed Manav Rachna University Faridabad B.Tech {Hons.} Electronics and Communication Engineering - VLSI Design & Technology fees, eligibility, admission dates, cutoff and ranking below.

Course HighlightsDetails
duration4 Years (Full Time)
mode of studyOn Campus
total fees₹ 10.26 Lakhs
median package₹ 4.5 Lakhs
eligibility10+2 +JEE MAINS
entrance testJEE Main

Manav Rachna University Faridabad Bachelor of Technology [B.Tech] ECE {Hons.}(Lateral Entry) - VLSI Design & Verification in Association with Truechip Fees

Manav Rachna University Faridabad B.Tech {Hons.} Electronics and Communication Engineering - VLSI Design & Technology fees 2026 is ₹ 10.26 Lakhs for the entire course duration.

  • This includes a total tuition fee of ₹ 10.26 Lakhs.
  • Candidates need to pay ₹ 2.57 Lakhs in the first year.
  • Manav Rachna University Faridabad Hostel Fee is ₹ 1.6 Lakhs.
Quota:
Fee TypeTotal Amount (INR)
total academic fee₹10.26 Lakhs
hostel fee₹6.42 Lakhs
total fee₹16.68 Lakhs
* Fees is refundable

Important Dates for Bachelor of Technology [B.Tech] ECE {Hons.}(Lateral Entry) - VLSI Design & Verification in Association with Truechip at Manav Rachna University Faridabad


Expired Events

EventsDates
JEE Main 2026 Result
Apr 20, 2026
JEE Main 2026 Exam Date
Apr 02, 2026 - Apr 09, 2026
Check entrance exam dates for admission in Bachelor of Technology [B.Tech] ECE {Hons.}(Lateral Entry) - VLSI Design & Verification in Association with Truechip at Manav Rachna University Faridabad -

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Manav Rachna University Faridabad Bachelor of Technology [B.Tech] ECE {Hons.}(Lateral Entry) - VLSI Design & Verification in Association with Truechip Admission Process

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