IIT Delhi M.Sc VLSI Design Tools & Technology: Fees 2026, Course Duration, Dates, Eligibility

Ans. Candidates need a valid GATE 2026 score in EC (Electronics and Communication Engineering) or EE (Electrical Engineering) to apply for M.S. VLSI Design Tools and Technology at IIT Delhi. The programme is offered through the Department of Electrical Engineering and CARE. IIT B.Tech graduates in Electronics or Electrical Engineering with CGPA 8.0 or above may be considered for exemption from the GATE requirement.

Ans. The programme covers semiconductor device modelling, VLSI circuit design, electronic design automation (EDA) tools, physical design, system-on-chip architecture, digital and mixed-signal design, and hardware verification. CARE at IIT Delhi focuses on applied microelectronics research with industrial relevance. Students work on thesis projects that span chip design flows, EDA algorithm development, or emerging topics in neuromorphic computing and low-power VLSI architectures.

Ans. Graduates find roles as VLSI design engineers, physical design engineers, verification engineers, and EDA tool developers at semiconductor and chip design companies. Major VLSI employers include Intel, Qualcomm, NVIDIA, Samsung Semiconductors, Synopsys, Cadence, and domestic firms like Sasken and CDAC. Many graduates also pursue Ph.D. programmes in VLSI, semiconductor design, or computer architecture at IITs and leading international universities.

Ans. Applicants need a B.E. or B.Tech in Electronics and Communication Engineering, Electrical Engineering, or a related discipline with at least 60% aggregate marks or CGPA 6.0/10. SC/ST/PwD candidates require a minimum of 55%. A valid GATE 2026 score in EC or EE is mandatory for general and OBC applicants. IIT B.Tech graduates with CGPA 8.0 or above may apply without a GATE score.

Ans. Yes, GATE-qualified M.S. students at IIT Delhi receive a Teaching Assistantship of INR 12,400 per month throughout the 2-year programme. This requires satisfactory academic performance and service as a teaching or laboratory assistant. SC/ST and PwD students are additionally exempt from tuition fee payment. Combined with the relatively low total academic fee of INR 1,57,600, the TA makes M.S. VLSI at IIT Delhi a cost-effective research qualification for GATE holders.

Ans. Shortlisted candidates are called to IIT Delhi for a written test and interview conducted by the Department of Electrical Engineering and CARE faculty. The test and interview assess knowledge of digital electronics, VLSI design principles, circuit theory, and semiconductor fundamentals. Candidates with prior exposure to EDA tools, FPGA design, or CMOS layout are at an advantage. Final selection is based on the written test, interview performance, and GATE score combined.